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PCB Reverse Engineering

High - speed Printed Circuit Board PCB Reverse Transmission Line Effect Analysis

 The alignment constitutes a loop that does not pass through the same network cable or other traces. If the loop through the same cable other lines constitute a closed loop. Both cases will form an antenna effect (line antenna and loop antenna)
1 method of suppressing electromagnetic interference and PCB Reverse
Minimizing the density of the outermost signal of the board is also a good way to reduce the electromagnetic radiation. A good solution to the signal integrity problem will improve the electromagnetic compatibility of the printed circuit board (EMC is very important to ensure that the printed circuit board is well It is a very effective method to adopt a signal layer with a signal layer for a complex design, and this method can be implemented using a "laminate" technology "Build-up" to make a printed circuit board. The laminate is achieved by adding a thin insulating layer on the common process printed circuit board and a combination of micropores for passing through these layers. The resistance and capacitance can be buried under the surface layer, and the alignment density per unit area is nearly doubled, Thus reducing the size of the printed circuit board.The reduction in printed circuit board area has a significant impact on the topological structure of the trace, which means a reduced current loop, a reduced branch trace length, and an electromagnetic radiation approximately proportional to the area of ​​the current loop ; While a small volume feature means that the high density pin package device can be used, which in turn causes the connection length to drop Current loop is reduced, improve the electromagnetic compatibility characteristics.
2 strictly control the length of the key line cable
It is necessary to take into account the existence of a transmission line effect on a printed circuit board. Now the widespread use of high clock frequency fast integrated circuit chip is the existence of such a problem. There are some basic principles to solve this problem: if you use CMOS or TTL circuit design, if the design of high-speed jump edge. Operating frequency less than 10MHz wiring length should not be greater than 7 inches. Operating frequency at 50MHz wiring length should not be greater than 1.5 inches. If the operating frequency reaches or exceeds 75MHz the wiring length should be 1 inch. The maximum wiring length for GaA chips should be 0.3 inches. If you go beyond this specification, there is a problem with the transmission line.
3 rational planning of the topology of the alignment
Another way to solve the transmission line effect is to select the correct routing path and terminal topology unless the length of the trace branch is kept short. The topology of the trace is the wiring order and wiring structure of a network cable. When using high-speed logic devices. Otherwise the fast-changing signal at the edge will be distorted by the branch line on the signal trunk line. Typically, printed circuit board routing uses two basic topologies, namely daisy chain (Daisi Chain cabling and star (Star distribution).
Wiring starts from the drive end, for daisy-chaining. In turn to reach the receiving end. If the series resistance is used to change the signal characteristics, the position of the series resistor should be close to the drive side. Control of the high-order harmonic interference, daisy-chaining the best results. But this way to pass the lowest rate of cloth, not easy to 100% cloth pass. In the actual design, the length of the daisy-chained branches is as short as possible, and the length of the peace should be Stub Delai <= Trt * 0.1.
The length of the branch in the high-speed TTL circuit PCB Reverse should be less than 1.5 inches. This topology occupies less cabling space and can be terminated with a single resistor match. But this alignment structure makes the reception of signals at different signal terminals are not synchronized, for example
But it is very difficult to manually route the printed circuit board with a high density. The use of automatic wiring is the best way to complete star wiring. Each terminal requires a terminating resistor. The resistance of the terminating resistor should match the characteristic impedance of the connection. This can be calculated by hand, star topology can effectively prevent the clock signal is not synchronized problem. The characteristic impedance value and the terminal matching resistance value can also be calculated by the CAD tool.
In practice, you can choose to use more complex matching terminals. The first option is the RC matching terminal. RC matching terminals can reduce power consumption, and the above two examples use a simple terminating resistor. But can only be used in the signal work more stable situation. This method is best suited for matching the clock line signal. The disadvantage is that the RC matching terminal in the capacitor may affect the signal shape and propagation speed.
But will slow down the signal transmission. This mode is used for bus delay circuits that have little effect on time delay. The advantage of the series resistance matching terminal is that it can reduce the number of board devices used and the connection density. The series resistance matching terminal does not generate additional power consumption.
This way the matching element needs to be placed near the receiving end. The advantage is not to pull down the signal, and can be very good to prevent noise. Typical for TTL input signals (ACT, the last way for the separation of matching terminals. HCT, FAST
For the terminal matching resistor package type and installation type must also be considered. Usually the SMD mounting resistor has a lower inductance than the via element, in addition. So SMD package components become preferred. If you choose the ordinary plug-in resistance also has two kinds of installation options: vertical and horizontal mode.
Can reduce the resistance and the resistance between the circuit board, the vertical device in a resistance to the installation of a very short pin. So that the heat resistance is more easily distributed to the air. But longer vertical devices will increase the inductance of the resistor. Horizontal device mode due to lower mounting lower inductance. But the overheat resistance will drift, the worst case resistance becomes open, causing the printed circuit board to end the match failure, become a potential failure factor.
4 Other available techniques
A decoupling capacitor should be added to the integrated circuit chip. This effectively removes the effects of the burrs on the power supply and reduces the radiation of the power supply loop on the PCB. To reduce the instantaneous overshoot of the voltage on the integrated circuit chip power supply.
Its smooth burr the best. This is why there are some device sockets with a decoupling capacitor when the decoupling capacitor is connected directly to the power supply leg of the integrated circuit instead of being connected to the power supply layer. While some devices require decoupling capacitors from the device to be sufficiently small.
Any high-speed and high-power devices should be placed together as much as possible to reduce the power supply voltage transient overshoot.
So long the power connection will form a loop between the signal and the circuit, if there is no power layer. Become a radiation source and susceptible circuit.



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